Coarse tuning for fractional-N synthesizers
US6710664B2 · kind B2 · utility
30Cited by
7References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.