Three-state binary adders with endpoint correction and methods of operating the same
US6710732B1 · kind B1 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 12, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Three-state binary adders with endpoint correction are employed in a digital signal processing system within a pipelined analog-to-digital converter. The adder is operable to add received signals. The endpoint correction circuitry, which is associated with the adder, is operable to (i) use ±½ full scale tip voltages and to (ii) generate over and under indicators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.