Parallel AD converter
US6710734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2003 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interpolation parallel AD converter is provided in which a switch is installed at each pre-amplifier in a first pre-amplifier array for selectively short-circuiting a portion between a comparison input end and a reference input end thereof, while a load transistor, a switch for selectively diode-connecting the load transistor, and a capacitor for keeping a voltage when the load transistor is diode-connected are installed in a pre-amplifier in a second pre-amplifier array. An offset occurring in each pre-amplifier in the first pre-amplifier array is suppressed by a compression effect of using a gain difference between a reset mode and an amplification mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.