Phase locked loop employing a fractional frequency synthesizer as a variable oscillator
US6710951B1 · kind B1 · utility
155Cited by
19References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit is disclosed comprising a phase detector for generating a phase error between an input oscillating signal and an output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the phase error, wherein the FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the phase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.