Methods and memory structures using tunnel-junction device as control element
US6711045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electron…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.