Semiconductor memory with multiple timing loops
US6711092B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Oct 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory with multiple timing loops for optimizing memory access operations. A clock generator circuit is provided for generating an internal memory clock based on an external clock or an input signal transition supplied to the memory device. The internal memory clock is operable to provide a timing reference with respect to a memory access operation based on a plurality of address signals. A timing loop selector is operable to select a particular timing loop responsive to at least one access margin signal. A shutdown circuit generates an access shutdown signal based on the selected timing loop that is optimized for a memory device of particular size, speed, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.