Method and apparatus for an interleaved non-blocking packet buffer
US6711170B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1546
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Memory interleaving is performed to increase bandwidth of a common memory in a non-blocking switch. The switch receives packets from a plurality of ingress ports, stores the packets in the common memory, and forwards the packets to a plurality of egress ports. The common memory is physically divided into two banks to provide two way interleaving. Two way interleaving is performed by reading a packet to be forwarded to an egress port from one bank concurrently with writing a packet received from an ingress port to the other bank. The common memory is physically divided into four banks to provide four way interleaving. Four way interleaving is performed by concurrently reading and writing two even banks or two odd banks. Bank balancing techniques are also provided to keep the banks of the common memory at the same level of occupancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.