Multi-rate clock generator and multi-rate digital data reproducing device
US6711228B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jul 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In order to construct a PLL circuit corresponding to the plurality of reproduction channel rates by using only a digital loop filter, the generation of a clock in accordance with the reproduction signal, of which the reproduction channel rate varies, is implemented with only one voltage control oscillator 7 in the case when the channel rate of the reproduction signal reproduced from the reproducer 1 varies at n/m of the basic channel rate at the time of recording by allowing the divider 6 to convert the output of the voltage control oscillator 7, which oscillates at the basic channel rate, into a reproduction clock through the n/m division. The control signal for controlling the voltage control oscillator 7 is generated through the phase error detector 3 and the digital loop filter 4, and by constructing this digital loop filter 4 with a digital filter which processes using the reproduction clock gained through the n/m division, a PLL circuit with an equal loop delay and loop sensitivity for any data rate can be implemented where, even in the case that the reproduction channel rate varies at a ratio of n/m, the frequency characteristics vary in a similar manner accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.