Duty-cycle adjustable clock generator with low reverse bias and zero DC level
US6711360B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J14/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty-cycle adjustable clock generator is disclosed. Combining a fundamental sinusoidal waveform with its phase-locked second harmonic waveform generates the duty-cycle adjustable clock waveform. The clock generator maintains zero DC level and minimum reverse bias voltage swing at high microwave and millimeter wave frequencies. Proper phase shift between the fundamental and second harmonic waveforms produces the desired clock waveform. The duty-cycle is controlled by the magnitude ratio of the fundamental and phase-locked second harmonic waveforms. Due to the resulting zero DC level and minimum reverse bias voltage over the duty-cycle adjustable range, the duty-cycle adjustable clock generator can be effectively used in various microwave and optical communication systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.