System and method for processor bus termination
US6711639B1 · kind B1 · utility
13Cited by
17References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for terminating the processor bus of a computer system is provided in which an external termination resistor is coupled between the processor and power at the optional processor socket. The placement of an external resistor at this location permits the termination of the bus irrespective of whether the computer system is configured to operate as a single processor system or a dual processor system. The value of external resistor is set to establish an impedance matching condition along the length of the processor bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.