Method and apparatus for accelerating input/output processing using cache injections
US6711650B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Nov 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.