Flexible mechanism for enforcing coherency among caching structures
US6711653B1 · kind B1 · utility
21Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a computer system that is capable of operating in a first or second cache coherency mode according to the operating environment in which the computer system is booted to run. If the operating environment supports memory attribute aliasing (MAA), the computer system implements a cache coherency mechanism that supports MAA. If the operating environment does not support MAA, the computer system implements a cache coherency mechanism that does not support MAA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.