Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization
US6711720B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing speed and predicted power of integrated circuit designs includes creating a machine representation representing devices of the integrated circuit design, where for each device in a path of the integrated circuit the representation includes device size information and device type information. The device type information includes selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type. A genetic global optimization is then performed, wherein substitutions of both device type and device size are performed to create a population of individual states from at least one parent machine representation in each iteration. Members of the population at each iteration are evaluated for speed and power consumption; and survivor members are selected of the population based upon their scores. Survivor members become parent states of the next iteration; and upon completion of iterations a best survivor is selected, and the integrated circuit netlist is updated to correspond to the best optimized survivor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.