Methods and apparatuses for designing integrated circuits using automatic reallocation techniques
US6711729B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for designing an integrated circuit (IC). In one exemplary method, a hardware description language (HDL) code is compiled to produce a representation of logic, and a portion of this representation of logic is allocated to a first physical portion of an area of the IC. This portion is reallocated automatically, according to machine determined parameters, such that a modified portion of the representation is allocated to the first physical portion. Examples of this reallocating include moving logic between regions on the IC, replicating logic based on the regions of the IC, decomposing RTL instances into elements based on information concerning the regions, reducing logic path crossings of a region's boundaries, and assuring that the original allocation or the result of a reallocation can be accommodated by the first physical portion of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.