Hole grid array package and socket technology
US6713684B2 · kind B2 · utility
1Cited by
5References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Nov 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.