Electronic package with offset reference plane cutout
US6713853B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jul 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package, such as a ball grid array (“BGA”) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.