Surface mount solder method and apparatus for decoupling capacitance and process of making
US6713871B2 · kind B2 · utility
32Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 21, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/957
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.