Semiconductor device for wafer examination
US6714031B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor device that enables examination of a wafer in an initial stage to check whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like. A semiconductor device is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a required circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.