Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation
US6714039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.