Logic circuitry-implemented bus buffer
US6714051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Dec 4, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.