Method and apparatus for passive component minimization of connector pins in a computer system
US6714052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system, a passive component minimization of connector pins configuration includes a motherboard and daughterboard. The daughterboard includes a selection switch coupled via passive components to a single connector pin, according to a prescribed state of multiple states of the daughterboard. In one embodiment, the passive components include three series connected resistors collectively coupled to the daughterboard connector pin. The motherboard includes a supply voltage and pull-up resistor circuit coupled to a single connector pin, and further includes decoding circuitry coupled to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data. Responsive to a mating of the daughterboard connector pin with the motherboard connector pin, the decoding circuitry converts voltage level data present at the motherboard connector pin into binary data representative of a current state of the daughterboard as a function of the selection switch and passive components of the daughterboard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.