Fast set reset latch with complementary outputs having equal delay and duty cycle
US6714053B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For use in a strobed comparator circuit of the type comprising a decision circuit and a set-reset (SR) latch for holding an output of the decision circuit, an apparatus and method is disclosed for reducing output delay between two complementary output signals of the SR latch. During the reset phase of the SR latch, only one input to the SR latch changes state while the other input to the SR latch returns to its previous logic state. Information relating to the change of logic states of the decision circuit and of the SR latch is provided to two feed forward transistors that send the information directly to the SR latch output that is likely to have an output signal delay. The apparatus and method of the present invention causes the output signals of the SR latch to arrive at their respective output terminals at approximately the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.