Memory module with equal driver loading
US6714433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.