Placement and routing of circuits using a combined processing/buffer cell
US6714903B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1998 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Sep 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells. According to this aspect of the invention, one of the cells obtained from the cell library, referred to as a combined cell, includes (1) a signal processing circuit; (2) a buffer circuit for buffering a signal external to the integrated circuit in which the combined cell is to be included; and (3) layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.