Method and means for enhanced interpretive instruction execution for a new integrated communications adapter using a queued direct input-output device
US6714997B1 · kind B1 · utility
4Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2000 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and means to provide a mechanism by which a hypervisor can permit a real machine to interpretively execute certain I/O instructions independently of the value of an I-bit in the subchannel. This is necessary as the I-bit covers all I/O instructions that can be interpretively executed; however, there can be instances where the hypervisor cannot allow the interpretive execution of other I/O instructions but can permit the interpretive execution of the SIGA instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.