Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency
US6715035B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2000 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Feb 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.