Performance improvement of a write instruction of a non-inclusive hierarchical cache memory unit
US6715040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.