Systems and methods for multiport memory access in a multimaster environment
US6715042B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jun 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.