Memory access system
US6715104B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2001 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for accessing a memory organized in memorization subsystems or memory blocks, e.g. standard Dual In-line Memory Modules, wherein the words to be stored are split into unitary elements so that several memorization subsystems are used to store one word and its associated Block Error Code (BEC) bits, is disclosed. The system includes a detector to detect a failure within a memorization subsystem. Insulator that are associated to each memorization subsystem insulate the failed memory block, and a new memorization subsystem is accessed in lieu of the failed one thanks to identification device which determine an available unfailed memory block. The user may replace the failed memory block without shutting down the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.