Method for fabricating a wiring line assembly for a thin film transistor array panel substrate
US6716660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The gate line assembly comprises a gate electrode and a gate line. A data line assembly crosses over the gate line assembly while being insulated from the gate line assembly. The data line assembly comprises a source electrode, a drain electrode and a data line. A semiconductor layer contacts the source electrode and the drain electrode. The semiconductor layer forms a thin film transistor together with the gate electrode, the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.