Method of forming memory arrays based on a triple-polysilicon source-side injection non-volatile memory cell
US6716700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2003 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.