Level shift circuit having at least two separate signal paths
US6717453B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit (100) that may have reduced input-output timing differences has been disclosed. Level shift circuit (100) may include a level shift portion (1) and a signal selection portion (2). Level shift portion (1) may receive an input signal at an input terminal (A) operating at a first voltage (VDD1) and may provide complementary signals at terminals (14 and 15) operating at a second voltage (VDD2). Signal selection circuit (2) may include a first signal propagation path (23 and 21) for timing an output signal at an output terminal (Y) based on a signal at terminal (14) and a second signal propagation path (22) for timing an output signal at an output terminal (Y) based on a signal at terminal (15). The first signal propagation path may be selected when a signal at terminal (14) transitions from high to low and the second signal propagation path may be selected when a signal at terminal (15) transitions from high to low. In this way, a delay difference caused by differences in timings of a rising edge and a falling edge of a signal may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.