Fast-acquisition phase-locked loop
US6717475B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides techniques for compensating for current leakage from a loop filter during off times of a PLL between on times of the PLL, e.g., when a cell phone is in paging mode. The leakage current is compensated by providing offsetting charge to ensure that the VCO tuning voltage when the PLL is turned from “off” to “on” is at or near the VCO tuning voltage when the PLL is locked (the VCO-lock voltage). Several techniques can be used compensate for the leakage current and several techniques can be used to determine how accurately the leakage current is being compensated for, and what, if any, adjustments to make in the offsetting charge to adequately compensate for the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.