Fast low cost multiple sensor readout system
US6717541B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/05
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A low resolution data acquisition system is presented. The data acquisition system has a plurality of readout modules serially connected to a controller. Each readout module has a FPGA in communication with analog to digital (A/D) converters, which are connected to sensors. The A/D converter has eight bit or lower resolution. The FPGA detects when a command is addressed to it and commands the A/D converters to convert analog sensor data into digital data. The digital data is sent on a high speed serial communication bus to the controller. A graphical display is used in one embodiment to indicate if a sensor reading is outside of a predetermined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.