Data processor having unified memory architecture providing priority memory access
US6717583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Jan 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/128
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.