Method to reduce bus voltage stress in a single-stage single switch power factor correction circuit
US6717826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus and method for reducing the voltage stress in a single-stage single-switch (SSSS) converter by modulating the predetermined operating frequency of the converter lower responsive to increasing voltage stress. A control circuit (116) and associated cooperable frequency setting capacitance (CT) and resistance (RT) are coupled to the primary circuit (112) and the secondary circuit (114) of the SSSS converter via a switch (120). A frequency foldback device (180) is coupled to CT or RT and cooperable therewith to lower bus voltage stress by modulating the switch frequency. The operating frequency is modulated (i.e. reduced) from the predetermined operating frequency upon detection of a voltage threshold transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.