Asic system architecture including data aggregation technique
US6718411B2 · kind B2 · utility
3Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.