Cache memory apparatus and central processor, hand-held device and arithmetic processor using the same
US6718426B2 · kind B2 · utility
4Cited by
2References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 26, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.