Parallel pack instruction method and apparatus
US6718456B1 · kind B1 · utility
2Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Mar 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.