Method and system for responding to a failed bus operation in an information processing system
US6718488B1 · kind B1 · utility
7Cited by
12References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an information processing system, a failed bus operation is detected. In response to the detecting, a primary power plan is cycled in the information processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.