Method and apparatus for analyzing inductive effects in a circuit layout
US6718530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to determine a noise and propagation delay effect through the given net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.