Integrated circuit inductor structure and non-destructive etch depth measurement
US6720229B2 · kind B2 · utility
21Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Apr 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.