Method of calibrating an analog-to-digital converter and a circuit implementing the same
US6720895B2 · kind B2 · utility
16Cited by
9References
15Claims
0Family size
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Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Feb 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/447
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of calibrating a high-speed analog to digital converter and an ADC that implements the method. Multiple linear regression analysis is used to calibrate the stages of a pipeline ADC to compensate for variations in gain from stage to stage and optionally to compensate for harmonic distortion. Current amplifiers each having gain of about 1.6 are used for low power consumption, minimal surface area requirements, and rapid sampling speed. Weighting factors are stored in lookup tables to minimize the number of adders required to generate the output digital word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.