Interpolation circuit having a conversion error connection range for higher-order bits and A/D conversion circuit utilizing the same
US6720901B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Jun 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interpolation circuit for generating interpolation and extrapolation differential voltages to a first and second differential input voltages, comprises a first and second differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal and their respective non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the non-inverted output terminals of the first and second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array. The interpolation circuit further comprises a third voltage dividing element array disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, so that at least a pair of extrapolation di…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.