Area efficient, low power and flexible time digitizer
US6720959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-linear time digitizer delay chain and a respective lookup table for converting the phase error into a digital code together prevent a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the phase error pulse associated with a digital phase lock loop (PLL) can be measured and represented in more meaningful and accurate ways that that achievable when using a conventional T2d circuit to convert the phase error into a digital code. The lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.