Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces
US6721212B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Jan 2, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.