Memory addressing structural test
US6721216B2 · kind B2 · utility
5Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.