Transmitter architectures for communications systems
US6721368B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2000 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Mar 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7239
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or the entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.