Method of mapping multiple address spaces into single PCI bus
US6721839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Apr 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination bus uses a respective predefined value (−X1, −X2, or −X3) for the shifted back address to the original address for completing the operation on the destination bus. Using the shifted address on the single bus utilizes a dual address cycle (DAC) of the single bus for the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.