Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory
US6721840B1 · kind B1 · utility
35Cited by
73References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.